1. Field of the Invention
The present invention generally relates to a storage device provided to, for example, the input end of a data processing apparatus for processing successively input data sequences, and more particularly, to a storage device configured to store data while compressing data items with the same input value.
2. Description of the Related Art
In data processing apparatuses for processing successively input data sequences, the internal data processing circuit may often require more time than the data supply interval. In order to absorb the difference between the data supply interval (or rate) and the data processing time (or rate), a first-in-first-out (FIFO) memory is generally provided at the input end of the data processing apparatus.
JP 9-274599A discloses a buffer memory aiming at efficient memory use, eliminating the necessity of writing all of the same data successively input to the processing apparatus in the FIFO memory.
Even if a FIFO memory is provided at the input end of the processing apparatus, the FIFO memory itself becomes full when the transmission rate of the input data sequences is greater than the data processing rate of the internal circuit. In this case, the operation of the data supply unit for supplying the data sequences to the data processing apparatus has to be suspended.
In order to prevent the suspension of the data supply unit from further causing other devices to temporarily suspend their operations, a queuing mechanism has to be provided to each of such devices provided on the data supply side. Alternatively, for those devices configured to finish the process when a prescribed time has passed (timeout expiration), it has to be guaranteed that the suspension time does not exceed the timeout period.
Meanwhile, the data sequences input from the data supply unit to the FIFO memory do not necessarily have to be output from the FIFO memory in the same order as the input order, that is, do not have to strictly comply with the transmission order. In addition, multiple data sequences from the data supply unit may be put together, and one data item may be supplied from the FIFO memory to the next-stage processing unit. In such a case, the data item is often in the correct data format for processing in the processing unit.
However, with the conventional techniques, if data are input to the FIFO memory exceeding the memory capacity, the overflow data are discarded, or alternatively, the discarded data are transmitted again to the FIFO memory.
If the overflow time in which the input data cannot be stored in the memory exceeds a prescribed time, or if the number of retransmissions of the discarded data exceeds a prescribed threshold, due to lack of storage space of the FIFO memory, the system may go down, depending on the system design. There is also a load distribution type data processing apparatus with multiple internal processing units provided to process different types of data sequences supplied from the data supply unit. In such an apparatus, if data sequences of the same type are continuously input, the workload cannot be distributed because data processing is carried out based solely on a specific type of data sequence.